1. Field of the Invention
The present invention relates to a semiconductor memory device such as a mask ROM (read only memory) and, more particularly, to a semiconductor memory device fabricated by using a layout technique for realizing the easy formation of memory cell diffused mask patterns and to a method for generating a ROM data pattern.
2. Description of the Related Art
FIG. 7 is a block diagram showing the structure of a mask ROM shown as an example of conventional semiconductor memory devices.
Such a semiconductor memory device comprises a memory cell array 20 where memory cell diffused mask patterns 21's are formed by using comb-shaped N-type MOS transistors, a control unit 3 which controls address signals and chip enabling signals from the outside, a row decoder 2 which selects a word line with a row address signal controlled by the control unit 3, and a column decoder 4 which selects a bit line with a column address signal controlled by the control unit 3.
Word lines 22's are connected to the gates of the memory cell transistors, and bit lines 23's are connected to the drains of the memory cell transistors via drain node contacts 24's. In addition, the sources of the memory cell transistors are connected to one after the other by using the memory cell diffused mask patterns 21's in the row direction in the memory cell array 20 and are grounded at the row decoder 2. The shape of the memory cell diffused mask patterns 21's is shown in FIG. 8.
As shown in FIG. 8, the conventional memory cell diffused mask patterns are formed in the shape of a comb in the row direction and repeatedly disposed in the column direction in the memory cell array 20. Through the adoption of such a structure, the contact-type mask ROM is fabricated in which the 2-bit memory cell transistors are formed by using one diffused mask pattern and the presence or absence of the drain node contact 24 is brought into correspondence with stored data “0” or “1”.
And furthermore, FIG. 9 is a schematic diagram made by taking a part from the memory cell array 20 of FIG. 7, which represents the memory cell diffused mask pattern 21 in the shape of the 2-bit comb-shaped diffused mask pattern, the word lines (n) 22a and (n−1) 22b connected to the gates of the memory cell transistors, and the bit lines (m−1) 23a, (m) 23b, and (m+1) 23c connected via the drain node contacts 24's to the drains of the memory cell transistors generated at the memory cell diffused mask pattern 21.
In such a structure, the sources of all the memory cell transistors are connected to one after the other via the diffused layer, i.e., the comb-shaped memory cell diffused pattern and has a ground potential as a source potential. Because of this, for example, when the word line (n) 22a has been selected by the row decoder 2 with a row address signal controlled by the control unit 3, the upper memory cell transistors of the comb-shaped memory cell diffused mask pattern 21 are turned on, the bit line (m) 23b of the memory cell to which the drain node contact 24 is disposed in advance comes to have the ground potential representing the source potential, and data “0” is read out in response to the selection of the bit line (m) 23b made by the column decoder 4 with a column address signal controlled by the control unit 3. On the other hand, the potential of the bit lines (m−1) 23a and (m+1) 23c for the memory cells to which such drain node contacts 24's are not disposed in advance remains at a precharge potential because the memory cell transistors are turned on but the source potential is not conveyed to the bit lines (m−1) 23a and (m+1) 23c due to the nondisposition of the drain node contacts 24's. Therefore, when the bit lines (m−1) 23a and (m+1) 23c have been selected by the column decoder 4 with a column address signal controlled by the control unit 3, data “1” is read out.
As described above, the sources of all the memory cell transistors are connected to one after the other via the diffused layer, i.e., the comb-shaped memory cell diffused patterns and have the ground potential as the source potential, and therefore when the word line (n−1) 22b has been selected by the row decoder 2 with a row address signal controlled by the control unit 3 as well, the lower memory cell transistors of the comb-shaped memory cell diffused mask pattern 21 are turned on. Then the bit lines (m−1) 23a, (m) 23b, and (m+1) 23c for the memory cells to which the drain node contacts 24's are disposed in advance come to have the ground potential representing the source potential. And furthermore, data “0” is read out in response to the selection of the bit line (m−1) 23a, (m) 23b, or (m+1) 23c made by the column decoder 4 with a column address signal controlled by the control unit 3.
As mentioned above, the memory cell diffused mask patterns are formed as the 2-bit comb-shaped patterns where the source nodes are shared in the row direction at the diffused layers (see JP-A No. 2004-342261).
In the conventional semiconductor memory device described above, because of the sharing of the sources of the memory cells, the memory cell diffused mask patterns are formed as the 2-bit comb-shaped diffused mask patterns where the wiring is made at the diffused layer.
However, in semiconductor memory devices having such a structure, the formation of the comb-shaped patterns has become difficult as semiconductor memory devices have become smaller in recent years, which has become the cause of the decreased yield of the semiconductor memory devices such as imbalance in the shape of memory cells and the malformation of memory cells.